Company news--Karmin Electronic (HK) Limited

Rapidus’ 2nm logic density can compete with TSMC and lead Intel 18A
2025-09-15

Foreign media wccftech quoted a user @ Kurnalsalts on social media platform "X" as saying that the 2nm (2HP) process of Japanese startup wafer foundry Rapidus will be able to compete with TSMC's 2nm (N2) process in logic density and will significantly defeat Intel 18A.

According to @ Kurnalsalts, the logic transistor density of Rapidus' 2nm process "2HP" is 237.31 MTr/mm ², which is comparable to TSMC's N2 with 236.17 MTr/mm ², and will significantly exceed Intel's 18A logic density of 184.21 MTr/mm ² (currently this data is only an estimate).

The user also revealed that the unit library involved in achieving this logic density for Rapidus 2HP includes an HD (high-density) library with a unit height of 138 units and a spacing of G45. Assuming that the numbers of Rapidus 2HP and TSMC N2 are similar, this indicates that both nodes are HD type cells with the goal of maximum logic density. Once the final solution is first unveiled, the number of transistors may be similar.

Although the logic transistor density of Intel 18A is relatively low, only about 184.21 MTr/mm ², this is mainly due to benchmark testing of Intel 18A using the HD library. Another factor contributing to the relatively low logic density of Intel 18A is the use of the latest Back Power On (BSPDN) technology, which occupies some of the front metal layers. This is why the logic density of Intel 18A in HD library measurements has decreased. Due to Intel's focus on performance/watt metrics, higher density is not the company's ultimate goal, especially since Intel 18A is primarily used for internal use.

If the logic density numbers of Rapidus' 2HP process are true, it also means that Rapidus has made significant progress in cutting-edge process technology. According to the plan, Rapidus' 2nm PDK will be available to customers in the first quarter of 2026 and is expected to enter mass production in 2027.

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