Domestic large model Kimi K3 can independently design AI chip: 45nm process with 100MHz frequency
2026-07-20
Since its release last night, the Kimi K3 model of the Dark Side of the Moon has gone viral both domestically and internationally. This 2.8 trillion parameter model's performance has almost caught up with the top American AI, including GPT-5.6 and Fable 5.

Various benchmark scores will no longer be included. It is worth noting that Kimi's official release listed several scenarios where K3 is used for real productivity, among which AI self-designed AI chips are a highlight.

According to Kimi, as an early proof of concept, Kimi K3 designed a chip to run a nano model built on its own architecture.

During 48 hours of continuous autonomous agent operation, K3 independently completed the construction, optimization, and validation of the chip based on open-source EDA tools and Nangate 45nm process library.

The chip has an area of 4mm ² and integrates 1.46 million standard cells, 0.277 MB SRAM, and INT4 MAC array with fused inverse quantization. It achieves timing convergence at 100MHz and continuously generates over 8700 tokens per second in simulation decoding throughput.

A chip designed by and serving models is a reflection of K3's long-range agent capabilities.

From the perspective of indicators, the chip designed by K3 has low specifications, with a 45nm process, 100MHz frequency, integrated 1.46 million standard units, and a cache of only 0.277MB, but the decoding throughput is good.
Designing chips with AI is currently one of the cutting-edge fields in AI. Several large model manufacturers have done this before with Kimi K3. K3 only spent 48 hours on verification this time. As we all know, the development of AI chips in reality is done on an annual basis, with a large amount of engineering resources invested and teams of hundreds or thousands of people continuously working.

The current level of AI intelligence is definitely not enough, but in the future, it will be essential to use AI to independently iterate software and hardware chips. It depends on which big model can be the first to produce engineering usable products in this area.