Company news--Karmin Electronic (HK) Limited

Implementation of Baiwei Storage Wafer Level Advanced Packaging and Testing Manufacturing Project
2023-12-01

According to BIWIN, recently, the wafer level advanced packaging and testing manufacturing project of Shenzhen Baiwei Storage Technology Co., Ltd. has officially landed in Dongguan Songshan Lake High tech Industrial Development Zone, and the signing ceremony was held in Dongguan City.

Baiwei Storage stated that the implementation of advanced wafer level packaging and testing projects is beneficial for the company's products to achieve larger bandwidth, higher speed, more flexible heterogeneous integration, and lower energy consumption, empowering customers in application fields such as mobile consumer electronics, high-end supercomputing, gaming, artificial intelligence, and the Internet of Things.

Baiwei Storage Master 16 Layer Die, 30-40 μ Advanced packaging technologies such as ultra-thin Die and multi chip heterogeneous integration provide support for the innovation and large-scale production of NAND, DRAM chips, and SiP packaging products.

At present, Belvedere Storage has built a professional wafer level advanced packaging technology and operation team with an organizational system and an international vision, and has reached strategic cooperation with Guangdong University of Technology to jointly build the State Key Laboratory of Precision Electronic Manufacturing Technology and Equipment (the major laboratory of Guangzhou Industrial Power) and other universities, so as to jointly promote the development of wafer level advanced packaging technology in the Greater Bay Area, enable project implementation and commercial success.

The advanced wafer level packaging and testing system is a semiconductor manufacturing intermediate process that falls between front-end wafer manufacturing and back-end packaging testing. It uses photolithography, etching, electroplating, PVD, CVD, CMP, Strip and other front-end wafer manufacturing processes to achieve bumping, rewiring, Fan in, Fan out, TSV and other process technologies, which not only directly package chips on the wafer, but also save physical space, It is also possible to integrate multiple chips on the same wafer, achieving higher integration levels. Advanced wafer level packaging and testing technology is one of the key development directions in the current semiconductor industry, and its widespread application will further promote the development and intelligence process of electronic devices.

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